The IMS A110 provides a solution to many real time image and signal processing problems by supporting techniques such as 1D/2D convolution/ correlation, statistical/histogram data collection and nonlinear data transformation. It is a cascadable, software configurable single chip digital signal processing device which operates at 20-MHz with a data throughput of 420 MOPS, and consists of three programmable length shift registers, a configurable 21 stage multiply accumulate array (MAC), a post processing unit (PPU) and a microprocessor interface. The chip is fabricated in a single level metal 1.2um polysilicide CMOS process and contains around 375k transistors on a 9.6mm×8.1mm die which translates to a site density of 4.1 tr/sq. mil. (excluding the pad ring). This paper will present an overview of the A110 architecture and highlight the key design techniques used to implement the multiply accumulate array.
|Original language||English (US)|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Dec 1 1989|
|Event||11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 - San Diego, CA, United States|
Duration: May 15 1989 → May 18 1989