Testability considerations

Shang Zhi Sun, David H C Du, Duen Ren Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations D1,1,2, extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? 2) Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
Editors Anon
PublisherIEEE
Pages97-100
Number of pages4
StatePublished - Dec 1 1994
EventProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA
Duration: Oct 10 1994Oct 12 1994

Other

OtherProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors
CityCambridge, MA, USA
Period10/10/9410/12/94

Fingerprint

Networks (circuits)
Merging

Cite this

Sun, S. Z., Du, D. H. C., & Liu, D. R. (1994). Testability considerations. In Anon (Ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 97-100). IEEE.

Testability considerations. / Sun, Shang Zhi; Du, David H C; Liu, Duen Ren.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. IEEE, 1994. p. 97-100.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sun, SZ, Du, DHC & Liu, DR 1994, Testability considerations. in Anon (ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, pp. 97-100, Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, 10/10/94.
Sun SZ, Du DHC, Liu DR. Testability considerations. In Anon, editor, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE. 1994. p. 97-100
Sun, Shang Zhi ; Du, David H C ; Liu, Duen Ren. / Testability considerations. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. editor / Anon. IEEE, 1994. pp. 97-100
@inproceedings{9d942cf0716c431c9b60bb9674bf1a4a,
title = "Testability considerations",
abstract = "Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100{\%} single fault testability, 100{\%} 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100{\%} 0-1 static sensitizability implies 100{\%} multi-fault testability, and that 100{\%} robust path delay fault testability implies 100{\%} multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100{\%} single-fault testability are presented. We further proved that the three transformations D1,1,2, extraction, De-Morgan keeping 100{\%} single fault testability also preserve 100{\%} multiple-fault testability, 100{\%} multi-fault testability, 100{\%} robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100{\%} multi-fault testability in a multiple outputs circuit not require 100{\%} 0-1 static sensitizability? 2) Does 100{\%} multi-fault testability in a single output circuit imply 100{\%} 0-1 static sensitizability?",
author = "Sun, {Shang Zhi} and Du, {David H C} and Liu, {Duen Ren}",
year = "1994",
month = "12",
day = "1",
language = "English (US)",
pages = "97--100",
editor = "Anon",
booktitle = "Proceedings - IEEE International Conference on Computer Design",
publisher = "IEEE",

}

TY - GEN

T1 - Testability considerations

AU - Sun, Shang Zhi

AU - Du, David H C

AU - Liu, Duen Ren

PY - 1994/12/1

Y1 - 1994/12/1

N2 - Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations D1,1,2, extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? 2) Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?

AB - Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations D1,1,2, extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? 2) Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?

UR - http://www.scopus.com/inward/record.url?scp=0028736054&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028736054&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028736054

SP - 97

EP - 100

BT - Proceedings - IEEE International Conference on Computer Design

A2 - Anon, null

PB - IEEE

ER -