Temporal Relaxation of Signal Temporal Logic Specifications for Resilient Control Synthesis

Ali Tevfik Buyukkocak, Derya Aksaray

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

We introduce a metric that can quantify the temporal relaxation of Signal Temporal Logic (STL) specifications and facilitate resilient control synthesis in the face of infeasibilities. The proposed metric quantifies a cumulative notion of relaxation among the subtasks, and minimizing it yields to structural changes in the original STL specification by i) modifying time-intervals, ii) removing subtasks entirely if needed. To this end, we formulate an optimal control problem that extracts state and input sequences by minimally violating the temporal requirements while achieving the desired predicates. We encode this problem in the form of a computationally efficient mixed-integer program. We show some theoretical results on the properties of the new metric. Finally, we present a case study of a robot that minimally violates the time constraints of desired tasks in the face of an infeasibility.

Original languageEnglish (US)
Title of host publication2022 IEEE 61st Conference on Decision and Control, CDC 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2890-2896
Number of pages7
ISBN (Electronic)9781665467612
DOIs
StatePublished - 2022
Event61st IEEE Conference on Decision and Control, CDC 2022 - Cancun, Mexico
Duration: Dec 6 2022Dec 9 2022

Publication series

NameProceedings of the IEEE Conference on Decision and Control
Volume2022-December
ISSN (Print)0743-1546
ISSN (Electronic)2576-2370

Conference

Conference61st IEEE Conference on Decision and Control, CDC 2022
Country/TerritoryMexico
CityCancun
Period12/6/2212/9/22

Bibliographical note

Funding Information:
This work was partially supported by MnDRIVE Graduate Research Fellowship from the University of Minnesota.

Publisher Copyright:
© 2022 IEEE.

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