TY - JOUR
T1 - Temperature-aware stress-based migration modeling in IC design
T2 - Moving from theory to practice
AU - Rothe, Susann
AU - Lienig, Jens
AU - Sapatnekar, Sachin S.
N1 - Publisher Copyright:
© 2025 The Authors
PY - 2025/10
Y1 - 2025/10
N2 - Recent research has shown that current density-based models for electromigration (EM) lack precision and should be replaced by physics-based hydrostatic stress simulation. While this new approach is widely accepted in the research community, it has not yet found its way into mainstream IC design flows. This paper aims at bringing state-of-the-art stress-based EM modeling into practical IC design by first examining the reasons that prevent the use of stress modeling in today's verification flows, and then proposing solutions that address these obstacles. We present a method for extracting the necessary technology information from standard IC lifetime testing. The stress modeling approach is then used to calculate the lifetime for example structures based on equivalent RC circuits, using common IC design tools. We further verify this approach by implementing reservoirs for extending interconnect lifetime. Additionally, this paper introduces the effect of local temperature variation and its impact on stress evolution. It is shown how equivalent RC circuits can be extended to also model the impact of local temperature on EM. Finally, we implement thermal migration (TM) into the equivalent RC circuits.
AB - Recent research has shown that current density-based models for electromigration (EM) lack precision and should be replaced by physics-based hydrostatic stress simulation. While this new approach is widely accepted in the research community, it has not yet found its way into mainstream IC design flows. This paper aims at bringing state-of-the-art stress-based EM modeling into practical IC design by first examining the reasons that prevent the use of stress modeling in today's verification flows, and then proposing solutions that address these obstacles. We present a method for extracting the necessary technology information from standard IC lifetime testing. The stress modeling approach is then used to calculate the lifetime for example structures based on equivalent RC circuits, using common IC design tools. We further verify this approach by implementing reservoirs for extending interconnect lifetime. Additionally, this paper introduces the effect of local temperature variation and its impact on stress evolution. It is shown how equivalent RC circuits can be extended to also model the impact of local temperature on EM. Finally, we implement thermal migration (TM) into the equivalent RC circuits.
KW - Electromigration
KW - Equivalent RC circuits
KW - Interconnect reliability
KW - SPICE
KW - Temperature
KW - Thermal migration
UR - https://www.scopus.com/pages/publications/105009899587
UR - https://www.scopus.com/pages/publications/105009899587#tab=citedBy
U2 - 10.1016/j.aeue.2025.155909
DO - 10.1016/j.aeue.2025.155909
M3 - Article
AN - SCOPUS:105009899587
SN - 1434-8411
VL - 200
JO - AEU - International Journal of Electronics and Communications
JF - AEU - International Journal of Electronics and Communications
M1 - 155909
ER -