Temperature-aware routing in 3D ICs

Tianpei Zhang, Yong Zhan, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

78 Scopus citations

Abstract

Three-dimensional integrated circuits (3D ICs) provide an attractive solution for improving circuit performance. Such solutions must be embedded in an electrothermally-conscious design methodology, since 3D ICs generate a significant amount of heat per unit volume. In this paper, we propose a temperature-aware 3D global routing algorithm with insertion of "thermal vias" and "thermal wires" to lower the effective thermal resistance of the material, thereby reducing chip temperature. Since thermal vias and thermal wires take up lateral routing space, our algorithm utilizes sensitivity analysis to judiciously allocate their usage, and iteratively resolve contention between routing and thermal vias and thermal wires. Experimental results show that our routing algorithm can effectively reduce the peak temperature and alleviate routing congestion.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2006
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2006
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages309-314
Number of pages6
ISBN (Print)0780394518, 9780780394513
DOIs
StatePublished - 2006
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
Duration: Jan 24 2006Jan 27 2006

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2006

Other

OtherASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CountryJapan
CityYokohama
Period1/24/061/27/06

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