Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high-quality, accurate thermal modeling and analysis, and thermally oriented placement optimizations, are essential prior to tapeout. This paper first presents an overview of thermal modeling and simulation methods, such as finite-difference time domain, finite element, model reduction, random walk, and Green-function based algorithms, that are appropriate for use in placement algorithms. Next, two-dimensional and three-dimensional thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described.
Bibliographical noteFunding Information:
Prof. Chen served as the program committee and/or organizer of the DAC, ICCAD, DATE, ISPD, ASPDAC, ISQED, SASIMI, VLSI/Computer-Aided Design (CAD) Symposium, and ITRS. He was the recipient of the D2000 Award presented by the Intel Corporation and the National Sciences Foundation Faculty Early Career Development Award (CAREER) in 1999 and 2001, respectively. He was also the recipient of the 2002 SIGDA/Association for Computing Machinery (ACM) Outstanding Young Faculty Award and the 2002 IBM Peter Schneider Faculty Development Award.
Manuscript received February 1, 2005; revised February 22, 2006. This work was supported in part by the National Science Foundation under Award CCR-0205227, Award CCF-0541367, Award CCR-0093309, and Award CCR-0204468, in part by the National Science Council of Taiwan, R.O.C., under Grant NSC 92-2218-E-002-030, and in part by the Semiconductor Research Corporation under Grant 2003-TJ-1092. J.-L. Tsai is with the University of Wisconsin, Madison, WI 53706 USA. C. C.-P. Chen is with the National Taiwan University, Taipei, Taiwan 10617, R.O.C. (e-mail: email@example.com). G. Chen, B. Goplen, H. Qian, Y. Zhan, and S. S. Sapatnekar are with the University of Minnesota, Minneapolis, MN 55455 USA. S.-M. Kang is with the University of California, Santa Cruz, CA 95064 USA. M. D. F. Wong is with the University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA.
Prof. Sapatnekar has held positions on the editorial board of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS IIVEXPRESS BRIEFS, IEEE Design and Test, and the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. He has served on the Technical Program Committee for various conferences, and as Technical Program and General Chair for Tau and ISPD, and Techical Program cochair for DAC. He has been a Distinguished Visitor for the IEEE Computer Society and a Distinguished Lecturer for the IEEE Circuits and Systems Society. He is a recipient of the National Science Foundation Career Award, three best paper awards at DAC and one at ICCD, and the SRC Technical Excellence Award.
- Physical design
- Thermal analysis
- Thermal simulation