TY - JOUR

T1 - Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

AU - Karandikar, S. K.

AU - Sapatnekar, Sachin S

PY - 2001/1/1

Y1 - 2001/1/1

N2 - We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is Silicon on Insulator (SOI). SOI devices exhibit an effect known as Parasitic Bipolar Effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid the PBE, such as transistor reordering, altering the way transistors are organized into gates, and adding pmos discharge transistors. We minimize the total cost of implementation, which includes the discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors needed by 44.23% and reduces the size of the final solution by 11.66% on average.

AB - We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is Silicon on Insulator (SOI). SOI devices exhibit an effect known as Parasitic Bipolar Effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid the PBE, such as transistor reordering, altering the way transistors are organized into gates, and adding pmos discharge transistors. We minimize the total cost of implementation, which includes the discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors needed by 44.23% and reduces the size of the final solution by 11.66% on average.

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M3 - Article

AN - SCOPUS:0034848150

SN - 0738-100X

SP - 377

EP - 382

JO - Proceedings - Design Automation Conference

JF - Proceedings - Design Automation Conference

ER -