Technology mapping for high-performance static CMOS and pass transistor logic designs

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji

Research output: Contribution to journalArticlepeer-review

14 Scopus citations


Two new techniques for mapping circuits are proposed in this paper. The first method, called the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the static CMOS/pass transistor logic (PTL) method, uses a mix of static CMOS and PTL to realize the circuit and utilizes the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all of the ISCAS'85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on different libraries shows an average delay reduction above 18% for OTR, and an average delay reduction above 35% for the static CMOS/PTL method, with significant savings in the area.

Original languageEnglish (US)
Pages (from-to)577-589
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number5
StatePublished - Oct 2001

Bibliographical note

Funding Information:
Manuscript received August 1, 1998; revised February 13, 2001. This work was supported in part by a Lucent Technologies DAC Graduate Scholarship, a gift from Intel Corporation, and the NSF under Contracts MIP-9502556 and MIP-9796305.


  • Physical design
  • Technology mapping


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