Technical perspective: Where the chips may fall

Circuit speed or timing, is one of the most crucial specifications on the performance of an integrated circuit. A chip may be unable to simultaneously meet the stringent set of delay and power specifications imposed upon it. On the other hand, insufficiently conservative margins may imply that a large number of manufactured chips will fail to meet specifications, resulting in yield losses that could sink a product, or a company. A paper by Orshansky and Wang presents the idea to use bounding techniques to capture the probability distribution of the circuit delay. This work supports Slepian's inequality, a classical result in probability theory, that allows a correlated normally distributed function to be bounded, and brings in the idea of stochastic majorization, which enables a partial ordering to be established on stochastic inequalities. This approach is applied to find the cumulative distribution function (CDF) of the maximum delay of a set of paths, and applied to standard benchmark circuits.