Teaching digital design in a programmable logic device arena

Christopher R. Carroll

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


Programmable logic devices have revolutionized the way in which digital circuits are built. FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices) have become the standards for implementing digital systems. FPGAs and CPLDs offer much higher circuit density, improved reliability, and fewer system components when compared with traditional digital design using discrete small-scale or medium-scale integrated circuits, all of which make programmable logic devices very attractive to the digital designer. However, these devices hide important details involved in understanding digital fundamentals, and the resulting hardware is really more of a computer-generated black box than it is a carefully crafted, finetuned design. Creativity in the design is less visible when using FPGAs or CPLDs, and designers are not rewarded as satisfyingly for "elegant" solutions to design problems. FPGAs and CPLDs implement solutions to digital design problems quickly and economically, both qualities that are important in an industrial setting. However, in an educational setting, the solution is not as important as understanding how the solution is reached, and these programmable devices automate and hide that process, making them less attractive as educational tools. Teaching digital design in a programmable logic device arena requires the instructor to inform students what is going on behind the scenes in the synthesis software. Otherwise, digital design degenerates into just another programming exercise, albeit using a hardware description language rather than traditional software languages. During Fall semester 2011, programmable logic devices were used for the first time1 as the basis for lab exercises in a second semester, advanced digital design laboratory at UMD, replacing design using discrete digital integrated circuits. The experience exposed some limitations imposed by the technology. For example, when circuits must avoid logic hazards (momentary "glitches" during transitions) as in asynchronous finite state machine design, FPGAs cannot be used properly, and CPLDs must be coerced into working by clumsily "fooling" the synthesis software. These specific digital circuit designs cannot be mapped cleanly to programmable devices without some innovative techniques. This paper reveals some of the author's experiences in adapting his digital design laboratory to the programmable logic device arena. Programmable logic devices, though attractive to the experienced designer, can be awkward to use in certain educational settings. Digital design instructors must be aware of their limitations. Instructors must find creative ways around the limitations, and must restrain themselves from being brainwashed by the glitz of FPGAs and CPLDs. This paper identifies techniques for maintaining the excitement and rewards of creative digital design within the confined restrictions of a programmable logic device arena.

Original languageEnglish (US)
Title of host publication119th ASEE Annual Conference and Exposition
PublisherAmerican Society for Engineering Education
ISBN (Print)9780878232413
StatePublished - 2012
Event119th ASEE Annual Conference and Exposition - San Antonio, TX, United States
Duration: Jun 10 2012Jun 13 2012

Publication series

NameASEE Annual Conference and Exposition, Conference Proceedings
ISSN (Electronic)2153-5965


Other119th ASEE Annual Conference and Exposition
Country/TerritoryUnited States
CitySan Antonio, TX


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