Keyphrases
Silica
100%
Transistor
100%
Probe-based
100%
Gate Dielectric Layer
100%
Modeling Experiment
100%
Modeling Prediction
100%
Dielectric Stack
100%
HfSiON
100%
Stress-induced
50%
Gate Dielectric
50%
Leakage Current
50%
Percolation Model
50%
HfO2
50%
Stress Conditions
50%
Probing Method
50%
Failure Time
50%
Simulation Methodology
50%
Gate Current
50%
Defect Formation
50%
Pre-existing Defects
50%
Induced Defects
50%
High Integration
50%
Integration Density
50%
Low Leakage Current
50%
Gate Leakage Current
50%
Current Characteristics
50%
Planar Device
50%
Metal Gate
50%
Current Integration
50%
Post-breakdown
50%
Engineering
Dielectrics
100%
Gate Dielectric
100%
Silicon Dioxide
100%
Dielectric Layer
66%
Measured Data
33%
High Integration Density
33%
Stress Condition
33%
Metal Gate
33%
Induced Defect
33%
Periodic Time
33%
Material Science
Dielectric Material
100%
Transistor
50%
Density
25%
Percolation
25%