Abstract
This paper addresses systematic synthesis of digital signal processing (DSP) data format converter architectures using minimum number of registers. Systematic life time analysis is used to calculate the minimum number of registers needed for the converter. The converter architecture can be synthesized using many possible register allocation schemes. We propose a novel forward-backward register allocation technique for the synthesis of the converter; this allocation technique requires less area for the implementation of control circuits than a simpler forward-circulate allocation scheme. Furthermore, the forward-backward allocation scheme guarantees completion and sustains the interframe pipelining rate, whereas the forward-circulate scheme does not guarantee completion of the allocation. Examples of data format converters studied in this paper include matrix transposers, and a general (m, d1) → (n, d2)[w] converter, which processes m words and d1bits per word in one input cycle and outputs n words and d2bits per word in each output cycle, and the word-length w is assumed to be a multiple of digit sizes d1and d2.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 423-440 |
| Number of pages | 18 |
| Journal | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |
| Volume | 39 |
| Issue number | 7 |
| DOIs | |
| State | Published - Jan 1 1992 |
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Systematic Synthesis of DSP Data Format Converters Using Life-Time Analysis and Forward-Backward Register Allocation. / Parhi, Keshab K.
In: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 39, No. 7, 01.01.1992, p. 423-440.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Systematic Synthesis of DSP Data Format Converters Using Life-Time Analysis and Forward-Backward Register Allocation
AU - Parhi, Keshab K
PY - 1992/1/1
Y1 - 1992/1/1
N2 - This paper addresses systematic synthesis of digital signal processing (DSP) data format converter architectures using minimum number of registers. Systematic life time analysis is used to calculate the minimum number of registers needed for the converter. The converter architecture can be synthesized using many possible register allocation schemes. We propose a novel forward-backward register allocation technique for the synthesis of the converter; this allocation technique requires less area for the implementation of control circuits than a simpler forward-circulate allocation scheme. Furthermore, the forward-backward allocation scheme guarantees completion and sustains the interframe pipelining rate, whereas the forward-circulate scheme does not guarantee completion of the allocation. Examples of data format converters studied in this paper include matrix transposers, and a general (m, d1) → (n, d2)[w] converter, which processes m words and d1bits per word in one input cycle and outputs n words and d2bits per word in each output cycle, and the word-length w is assumed to be a multiple of digit sizes d1and d2.
AB - This paper addresses systematic synthesis of digital signal processing (DSP) data format converter architectures using minimum number of registers. Systematic life time analysis is used to calculate the minimum number of registers needed for the converter. The converter architecture can be synthesized using many possible register allocation schemes. We propose a novel forward-backward register allocation technique for the synthesis of the converter; this allocation technique requires less area for the implementation of control circuits than a simpler forward-circulate allocation scheme. Furthermore, the forward-backward allocation scheme guarantees completion and sustains the interframe pipelining rate, whereas the forward-circulate scheme does not guarantee completion of the allocation. Examples of data format converters studied in this paper include matrix transposers, and a general (m, d1) → (n, d2)[w] converter, which processes m words and d1bits per word in one input cycle and outputs n words and d2bits per word in each output cycle, and the word-length w is assumed to be a multiple of digit sizes d1and d2.
UR - http://www.scopus.com/inward/record.url?scp=0026897642&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0026897642&partnerID=8YFLogxK
U2 - 10.1109/82.160168
DO - 10.1109/82.160168
M3 - Article
VL - 39
SP - 423
EP - 440
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-8328
IS - 7
ER -