Systematic design of architectures for M-ary tree-structured filter banks

Tracy C. Denk, Keshab K. Parhi

Research output: Contribution to conferencePaper

5 Scopus citations

Abstract

This paper presents an approach for systematically synthesizing VLSI architectures for M-ary tree-structured filter banks which are constructed from a prototype M-channel FIR filter bank. The resulting synchronous architecture is single-rate, i.e., the architecture uses a single clock even though it implements a multirate algorithm. We derive folding equations and use retiming for folding multirate systems to synthesize the control circuitry. A scheduling algorithm is presented which retimes the multirate filter bank to keep the memory requirements of the architecture low. Our approach can be used to design architectures for a wide variety of applications of full and pruned tree-structured filter banks including subband decompositions, discrete wavelet transforms, and computation of wavelet packet bases.

Original languageEnglish (US)
Pages157-166
Number of pages10
StatePublished - Dec 1 1995
EventProceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn
Duration: Oct 16 1995Oct 18 1995

Other

OtherProceedings of the 1995 IEEE Workshop on VLSI Signal Processing
CityOsaka, Jpn
Period10/16/9510/18/95

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    Denk, T. C., & Parhi, K. K. (1995). Systematic design of architectures for M-ary tree-structured filter banks. 157-166. Paper presented at Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing, Osaka, Jpn, .