This paper considers the design of low-complexity bit-parallel dedicated finite field multiplier. A systematic design approach of Mastrovito multiplier is proposed, which is applicable to GF(2m) generated by an arbitrary irreducible polynomial. This approach extensively exploits the spatial correlation of matrix elements in Mastrovito multiplication to reduce the complexity. The developed general Mastrovito multiplier is highly modular, which is desirable for VLSI hardware implementation. Meanwhile, the presented approach can be used to develop efficient Mastrovito multipliers for several special irreducible polynomials, such as trinomial and equally-spaced-polynomial, and further find some other special irreducible polynomials which can also lead to low-complexity multipliers.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - 2000|
|Event||2000 IEEE Workshop on Signal Processing Systems (SIPS 2000) - Lafayette, LA, USA|
Duration: Oct 11 2000 → Oct 13 2000