In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dynamic voltage-frequency scaling (DVFS) system. The impact of different task scheduling algorithms on the overall system power was also analyzed. We find that in a hypothetical 256-core processor, under a per-core DVFS assumption, the FIVR-based power delivery consumes 20% less power than the LDO-based one for a 50% throughput. However, as the number of cores in the processor reduces, the difference in power consumption between the FIVR-based and LDO-based power delivery schemes becomes smaller. For example, in the case of a 16-core processor with per-core DVFS capability, FIVR-based design was found to consume about the same power as the LDO-based design.
|Original language||English (US)|
|Number of pages||9|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Dec 2016|
Bibliographical noteFunding Information:
This work was supported by the U.S. Department of Energy, Office of Science, and the National Nuclear Security Administration through the FastFoward program at the Lawrence Livermore National Laboratory under Contract B600738.
© 2016 IEEE.
- Circuit simulation
- dynamic voltage scaling
- integrated circuit modeling
- multicore processing
- power dissipation
- switching converters