System-level design for test of fully differential analog circuits

Nicholas J. Stessman, Bapiraju Vinnakota, Ramesh Harjani

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

Several designs for test techniques for fully differential circuits have recently been proposed. These techniques are based on the inherent data encoding, the fully differential analog code (FDAC), present in differential circuits. These techniques have not previously been verified experimentally. In this paper, we report results from a fabricated test chip which incorporates design for test structures. The test chip is a fully differential fifth-order filter, and was fabricated on a 2-μm CMOS process. The test techniques implemented are derived from a system-level technique developed earlier. The test chip contains fault injection circuitry to emulate faults. Our results demonstrate that the FDAC is a viable design for test technique for analog circuits.

Original languageEnglish (US)
Pages (from-to)1526-1534
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume31
Issue number10
DOIs
StatePublished - Oct 1 1996

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