Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems

Vijay Sundararajan, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

In this paper, we formalize a novel multirate multidimensional folding (MMF) transformation, which is a tool used to systematically synthesize control circuits for pipelined very large scale integrated (VLSI) architectures that implement a restricted but immensely practical class, namely, rectangular decimators/expandors with line-by-line scan, of multirate multidimensional algorithms. Although multirate multidimensional algorithms contain decimators and expanders that change the effective sample rate of a discrete-time signal, it is possible using MMF to time multiplex the algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. MMF constraints are derived, and these constraints are used to address two related issues. The first issue is memory requirements in the folded architectures. We derive expressions for the minimum number of memory units required by a folded architecture that implements a multirate multidimensional algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints that indicate how a multirate multidimensional data flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of DSP applications that are based on multirate multidimensional algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms. Many design examples are considered to demonstrate the viability of MMF. It is shown that MMF is able to save 18-25% area for 1-4 level two-dimensional (2-D) dicrete wavelet trasforms (DWTs). A tradeoff between computational and storage area is highlighted by our study of a 2064 × 2064 4-level 2-D DWT. We also present a few 2-D IIR filter designs, where we are able to exploit the throughput bottleneck of these filters to derive extremely low area designs.

Original languageEnglish (US)
Pages (from-to)1954-1965
Number of pages12
JournalIEEE Transactions on Signal Processing
Volume51
Issue number7
DOIs
StatePublished - Jul 2003

Bibliographical note

Funding Information:
Manuscript received June 16, 1999; revised November 21, 2002. This work was supported by the Army Research Office under Grant DA/DAAH-94-G-0405. The associate editor coordinating the review of this paper and approving it for publication was Prof. Chaitali Chakrabarti.

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