Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply voltage for gates off the critical path it is possible to dramatically reduce power consumption in CMOS VLSI circuits without performance degradation. Interfacing gates operating under multiple supply voltages, however, requires the use of level converters, which makes the problem modeling difficult. In this paper we develop a formal model and develop an efficient heuristic for addressing the use of two supply voltages for low power CMOS VLSI circuits without performance degradation. Power consumption savings up to 25% over and above the best known existing heuristics are demonstrated for combinational circuits in the ISCAS85 benchmark suite.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - Design Automation Conference|
|State||Published - 1999|
|Event||Proceedings of the 1999 36th Annual Design Automation Conference (DAC) - New Orleans, LA, USA|
Duration: Jun 21 1999 → Jun 25 1999