In many DSP applications, data format converters (DFCs) are used to permute the data transferred between processing modules. In VLSI implementations, these converters consume a large amount of the given resources, especially area. Previous methods on synthesis of data format converters have focussed on optimizing the number of registers. Recently, two-dimensional register allocation schemes have been proposed to reduce the area of the DFCs. In this paper, we present another two-dimensional register allocation scheme where we not only try to optimize the number of registers but also reduce the number of interconnections by maximizing the reuse of the interconnections previously made during the synthesis procedure. Such a strategy also leads to reduction in the number of multiplexors used. We show that the proposed allocation scheme results in lower area DFCs than the previously proposed ones.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 1996|
|Event||Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA|
Duration: May 12 1996 → May 15 1996