Synthesis of folded multi-dimensional DSP systems

Vijay Sundararajan, Keshab K. Parhi

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

In this paper a novel multi-dimensional (MD) folding transformation technique is formalized which can be used to synthesize control circuits for pipelined architectures which implement a specific class of MD DSP algorithms. Feasibility constraints are derived for folding a 2-D single rate data-flow graph (DFG) onto an available set of hardware functional units according to a given schedule. Retiming is introduced as a tool to facilitate feasibility of the folding constraints and minimization of the storage requirements for the folded architecture. We also derive expressions for the exact storage requirements for the folded architecture. Detailed design example of a non-separable 2-D IIR filter is provided.

Original languageEnglish (US)
Pages (from-to)433-436
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
StatePublished - Jan 1 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: May 31 1998Jun 3 1998

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