Abstract
In this paper a novel multi-dimensional (MD) folding transformation technique is formalized which can be used to synthesize control circuits for pipelined architectures which implement a specific class of MD DSP algorithms. Feasibility constraints are derived for folding a 2-D single rate data-flow graph (DFG) onto an available set of hardware functional units according to a given schedule. Retiming is introduced as a tool to facilitate feasibility of the folding constraints and minimization of the storage requirements for the folded architecture. We also derive expressions for the exact storage requirements for the folded architecture. Detailed design example of a non-separable 2-D IIR filter is provided.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 433-436 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| State | Published - Jan 1 1998 |
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Synthesis of folded multi-dimensional DSP systems. / Sundararajan, Vijay; Parhi, Keshab K.
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 01.01.1998, p. 433-436.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Synthesis of folded multi-dimensional DSP systems
AU - Sundararajan, Vijay
AU - Parhi, Keshab K
PY - 1998/1/1
Y1 - 1998/1/1
N2 - In this paper a novel multi-dimensional (MD) folding transformation technique is formalized which can be used to synthesize control circuits for pipelined architectures which implement a specific class of MD DSP algorithms. Feasibility constraints are derived for folding a 2-D single rate data-flow graph (DFG) onto an available set of hardware functional units according to a given schedule. Retiming is introduced as a tool to facilitate feasibility of the folding constraints and minimization of the storage requirements for the folded architecture. We also derive expressions for the exact storage requirements for the folded architecture. Detailed design example of a non-separable 2-D IIR filter is provided.
AB - In this paper a novel multi-dimensional (MD) folding transformation technique is formalized which can be used to synthesize control circuits for pipelined architectures which implement a specific class of MD DSP algorithms. Feasibility constraints are derived for folding a 2-D single rate data-flow graph (DFG) onto an available set of hardware functional units according to a given schedule. Retiming is introduced as a tool to facilitate feasibility of the folding constraints and minimization of the storage requirements for the folded architecture. We also derive expressions for the exact storage requirements for the folded architecture. Detailed design example of a non-separable 2-D IIR filter is provided.
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UR - http://www.scopus.com/inward/citedby.url?scp=0031618674&partnerID=8YFLogxK
M3 - Article
VL - 2
SP - 433
EP - 436
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
ER -