In this paper a novel multi-dimensional (MD) folding transformation technique is formalized which can be used to synthesize control circuits for pipelined architectures which implement a specific class of MD DSP algorithms. Feasibility constraints are derived for folding a 2-D single rate data-flow graph (DFG) onto an available set of hardware functional units according to a given schedule. Retiming is introduced as a tool to facilitate feasibility of the folding constraints and minimization of the storage requirements for the folded architecture. We also derive expressions for the exact storage requirements for the folded architecture. Detailed design example of a non-separable 2-D IIR filter is provided.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 1998|
|Event||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
Duration: May 31 1998 → Jun 3 1998