Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing

Hua Tang; Hui Zhang; Alex Doboli

doi:10.1145/764808.764861

Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing

Hua Tang
, Hui Zhang
, Alex Doboli

Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.

Original language	English (US)
Pages (from-to)	207-210
Number of pages	4
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
DOIs	https://doi.org/10.1145/764808.764861
State	Published - 2003
Event	Proceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States Duration: Apr 28 2003 → Apr 29 2003

Keywords

Continuous-time filter
Synthesis
ΣΔ modulator

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10.1145/764808.764861

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abstract = "This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.",

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journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

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AU - Tang, Hua

AU - Zhang, Hui

AU - Doboli, Alex

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N2 - This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.

AB - This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.

KW - Continuous-time filter

KW - Synthesis

KW - ΣΔ modulator

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DO - 10.1145/764808.764861

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AN - SCOPUS:0038714051

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JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 2003 ACM Great Lakes Symposium on VLSI

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ER -

Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing

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Keywords

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