Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing

Hua Tang, Hui Zhang, Alex Doboli

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations

Abstract

This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.

Original languageEnglish (US)
Pages (from-to)207-210
Number of pages4
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
DOIs
StatePublished - 2003
EventProceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States
Duration: Apr 28 2003Apr 29 2003

Keywords

  • Continuous-time filter
  • Synthesis
  • ΣΔ modulator

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