Supporting speculative multithreading on simultaneous multithreaded processors

Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei Chung Hsu, Pen Chung Yew

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations


Speculative multithreading is a technique that has been used to improve single thread performance. Speculative multithreading architectures for Chip multiprocessors (CMPs) have been extensively studied. But there have been relatively few studies on the design of speculative multithreading for simultaneous multithreading (SMT) processors. The current SMT based designs - IMT [9] and DMT [2] use load/store queue (LSQ) to perform dependence checking. Since the size of the LSQ is limited, this design is suitable only for small threads. In this paper we present a novel cache-based architecture support for speculative simultaneous multithreading which can efficiently handle larger threads. In our architecture, the associativity in the cache is used to buffer speculative values. Our 4-thread architecture can achieve about 15% speedup when compared to the equivalent superscalar processors and about 3% speedup on the average over the LSQ-based architectures, however, with a less complex hardware. Also our scheme can perform 14% better than the LSQ-based scheme for larger threads.

Original languageEnglish (US)
Title of host publicationHigh Performance Computing - HiPC 2006 - 13th International Conference Proceedings
Number of pages11
StatePublished - 2006
Event13th International Conference on High Performance Computing, HiPC 2006 - Bangalore, India
Duration: Dec 18 2006Dec 21 2006

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4297 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other13th International Conference on High Performance Computing, HiPC 2006


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