Superassociative tagged cache coherence directory

David J Lilja, Shanthi Ambalavanan

Research output: Contribution to conferencePaperpeer-review

Abstract

Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in shared-memory multiprocessors. These directories use special-purpose caches of pointers that are subject to two types of overflow: 1) pointer overflow, which limits the maximum sharing of a memory block, and 2) set overflow, which forces the premature invalidation of cached blocks. We propose a superassociative tagged directory that can preserve some of the cached copies of a memory block when a set overflows by allowing multiple address tags in the same set to contain the same address value. Verilog descriptions are used to estimate its implementation cost and timing delay, and a multiprocessor cache simulator is used to evaluate its performance.

Original languageEnglish (US)
Pages42-45
Number of pages4
StatePublished - Dec 1 1994
EventProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA
Duration: Oct 10 1994Oct 12 1994

Other

OtherProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors
CityCambridge, MA, USA
Period10/10/9410/12/94

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