Abstract
Successive cancellation list (SCL) decoding algorithm is a powerful method that can help polar codes achieve excellent error-correcting performance. However, the current SCL algorithm and decoders are based on likelihood or log-likelihood forms, which render high hardware complexity. In this paper, we propose a log-likelihood-ratio (LLR)-based SCL (LLR-SCL) decoding algorithm, which only needs half the computation and storage complexity than the conventional one. Then, based on the proposed algorithm, we develop low-complexity VLSI architectures for LLR-SCL decoders. Analysis results show that the proposed LLR-SCL decoder achieves 50% reduction in hardware and 98% improvement in hardware efficiency.
| Original language | English (US) |
|---|---|
| Title of host publication | Conference Record of the 48th Asilomar Conference on Signals, Systems and Computers |
| Editors | Michael B. Matthews |
| Publisher | IEEE Computer Society |
| Pages | 548-552 |
| Number of pages | 5 |
| ISBN (Electronic) | 9781479982974 |
| DOIs | |
| State | Published - Apr 24 2015 |
| Event | 48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 - Pacific Grove, United States Duration: Nov 2 2014 → Nov 5 2014 |
Publication series
| Name | Conference Record - Asilomar Conference on Signals, Systems and Computers |
|---|---|
| Volume | 2015-April |
| ISSN (Print) | 1058-6393 |
Other
| Other | 48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 |
|---|---|
| Country/Territory | United States |
| City | Pacific Grove |
| Period | 11/2/14 → 11/5/14 |
Bibliographical note
Publisher Copyright:© 2014 IEEE.
Keywords
- Log-likelihood ratio (LLR)
- Low-complexity
- Polar codes
- Successive cancellation list (SCL)
- VLSI