Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing

John Keane, Hanyong Eom, Tae Hyoung Kim, Sachin S Sapatnekar, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

52 Scopus citations


Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold regime are significantly different from those in strong-inversion. This presents new challenges in design optimization, particularly in complex gates with stacks of transistors. In this paper, we demonstrate a new optimal sizing scheme for subthreshold designs which takes these issues into account. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single transistor with equivalent current drivability. Experimental results show that our framework provides a performance improvement of up to 13.5% over the conventional logical effort method on ISCAS benchmark circuits, while one component circuit demonstrated an improvement of 33.1%.

Original languageEnglish (US)
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Number of pages4
StatePublished - Dec 1 2006

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


  • Logical effort
  • Subthreshold logic
  • Ultra-low power design

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