Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control

Michael L. Geier, Pradyumna L. Prabhumirashi, Julian J. McMorrow, Weichao Xu, Jung Woo T. Seo, Ken Everaerts, Chris H. Kim, Tobin J. Marks, Mark C. Hersam

Research output: Contribution to journalArticlepeer-review

86 Scopus citations


In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

Original languageEnglish (US)
Pages (from-to)4810-4814
Number of pages5
JournalNano letters
Issue number10
StatePublished - Oct 9 2013


  • CMOS
  • NAND
  • NOR
  • inverter
  • transistor


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