Study of Nanowire-Based Integrated via Technology for CMOS Application in Millimeter-Wave Frequencies

Yali Zhang; Joseph Um; Bethanie Stadler; Rashaunda Henderson; Rhonda Franklin

doi:10.1109/lmwc.2021.3063548

Study of Nanowire-Based Integrated via Technology for CMOS Application in Millimeter-Wave Frequencies

Yali Zhang, Joseph Um, Bethanie Stadler, Rashaunda Henderson, Rhonda Franklin

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

This work shows a novel integrated via structure based on 1.2-μm thick copper nanowires (NWs) for use in CMOS applications at millimeter-wave frequencies. Coplanar waveguide (CPW) lines are fabricated on a 5000-Ω-cm high-resistivity silicon wafer and connected by NW vias that are grown in integrated anodized alumina oxide (AAO). The AAO layer is fabricated by anodizing an evaporated aluminum layer onto the silicon wafer. This cointegrated technology has 0.095-dB insertion loss for 0.3-mm long circuits with two vias at 40 GHz. The results are promising with an estimated loss per via of approximately 0.0275 dB. The fabricated structure shows great performance agreement with its reference test circuits of similar length. The design comparisons of circuits with different via dimensions and positions show that the shorter the via length, the wider the via width; and placing the via on the CPW ground plane closer to the signal line provides better performance.

Original language	English (US)
Article number	9369363
Pages (from-to)	693-696
Number of pages	4
Journal	IEEE Microwave and Wireless Components Letters
Volume	31
Issue number	6
DOIs	https://doi.org/10.1109/lmwc.2021.3063548
State	Published - Jun 1 2021

Bibliographical note

Funding Information:
Manuscript received February 22, 2021; accepted March 1, 2021. Date of publication March 4, 2021; date of current version June 7, 2021. This work was supported in part by the Semiconductor Research Corporation (SRC) and in part by the National Science Foundation (NSF) under Award 01762884 with portions conducted in the Minnesota Nano Center, which is supported by NSF through the National Nanotechnology Coordinated Infrastructure (NNCI) under Award ECCS-2025124. (Corresponding author: Yali Zhang.) Yali Zhang, Joseph Um, Bethanie Stadler, and Rhonda Franklin are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

Publisher Copyright:
© 2001-2012 IEEE.

Keywords

CMOS
integrated circuit (IC)
millimeter-wave technology
nanowires (NWs)

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10.1109/lmwc.2021.3063548

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title = "Study of Nanowire-Based Integrated via Technology for CMOS Application in Millimeter-Wave Frequencies",

abstract = "This work shows a novel integrated via structure based on 1.2-μm thick copper nanowires (NWs) for use in CMOS applications at millimeter-wave frequencies. Coplanar waveguide (CPW) lines are fabricated on a 5000-Ω-cm high-resistivity silicon wafer and connected by NW vias that are grown in integrated anodized alumina oxide (AAO). The AAO layer is fabricated by anodizing an evaporated aluminum layer onto the silicon wafer. This cointegrated technology has 0.095-dB insertion loss for 0.3-mm long circuits with two vias at 40 GHz. The results are promising with an estimated loss per via of approximately 0.0275 dB. The fabricated structure shows great performance agreement with its reference test circuits of similar length. The design comparisons of circuits with different via dimensions and positions show that the shorter the via length, the wider the via width; and placing the via on the CPW ground plane closer to the signal line provides better performance.",

keywords = "CMOS, integrated circuit (IC), millimeter-wave technology, nanowires (NWs)",

author = "Yali Zhang and Joseph Um and Bethanie Stadler and Rashaunda Henderson and Rhonda Franklin",

note = "Funding Information: Manuscript received February 22, 2021; accepted March 1, 2021. Date of publication March 4, 2021; date of current version June 7, 2021. This work was supported in part by the Semiconductor Research Corporation (SRC) and in part by the National Science Foundation (NSF) under Award 01762884 with portions conducted in the Minnesota Nano Center, which is supported by NSF through the National Nanotechnology Coordinated Infrastructure (NNCI) under Award ECCS-2025124. (Corresponding author: Yali Zhang.) Yali Zhang, Joseph Um, Bethanie Stadler, and Rhonda Franklin are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Publisher Copyright: {\textcopyright} 2001-2012 IEEE.",

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AU - Zhang, Yali

AU - Um, Joseph

AU - Stadler, Bethanie

AU - Henderson, Rashaunda

AU - Franklin, Rhonda

N1 - Funding Information: Manuscript received February 22, 2021; accepted March 1, 2021. Date of publication March 4, 2021; date of current version June 7, 2021. This work was supported in part by the Semiconductor Research Corporation (SRC) and in part by the National Science Foundation (NSF) under Award 01762884 with portions conducted in the Minnesota Nano Center, which is supported by NSF through the National Nanotechnology Coordinated Infrastructure (NNCI) under Award ECCS-2025124. (Corresponding author: Yali Zhang.) Yali Zhang, Joseph Um, Bethanie Stadler, and Rhonda Franklin are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Publisher Copyright: © 2001-2012 IEEE.

PY - 2021/6/1

Y1 - 2021/6/1

N2 - This work shows a novel integrated via structure based on 1.2-μm thick copper nanowires (NWs) for use in CMOS applications at millimeter-wave frequencies. Coplanar waveguide (CPW) lines are fabricated on a 5000-Ω-cm high-resistivity silicon wafer and connected by NW vias that are grown in integrated anodized alumina oxide (AAO). The AAO layer is fabricated by anodizing an evaporated aluminum layer onto the silicon wafer. This cointegrated technology has 0.095-dB insertion loss for 0.3-mm long circuits with two vias at 40 GHz. The results are promising with an estimated loss per via of approximately 0.0275 dB. The fabricated structure shows great performance agreement with its reference test circuits of similar length. The design comparisons of circuits with different via dimensions and positions show that the shorter the via length, the wider the via width; and placing the via on the CPW ground plane closer to the signal line provides better performance.

AB - This work shows a novel integrated via structure based on 1.2-μm thick copper nanowires (NWs) for use in CMOS applications at millimeter-wave frequencies. Coplanar waveguide (CPW) lines are fabricated on a 5000-Ω-cm high-resistivity silicon wafer and connected by NW vias that are grown in integrated anodized alumina oxide (AAO). The AAO layer is fabricated by anodizing an evaporated aluminum layer onto the silicon wafer. This cointegrated technology has 0.095-dB insertion loss for 0.3-mm long circuits with two vias at 40 GHz. The results are promising with an estimated loss per via of approximately 0.0275 dB. The fabricated structure shows great performance agreement with its reference test circuits of similar length. The design comparisons of circuits with different via dimensions and positions show that the shorter the via length, the wider the via width; and placing the via on the CPW ground plane closer to the signal line provides better performance.

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Study of Nanowire-Based Integrated via Technology for CMOS Application in Millimeter-Wave Frequencies

Abstract

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