Stress-induced performance shifts in 3d drams

Research output: Contribution to journalArticlepeer-review

Abstract

3D-stacked DRAMs can significantly increase cell density and bandwidth while also lowering power consumption. However, 3D structures experience significant thermomechanical stress due to the differential rate of contraction of the constituent materials, which have different coefficients of thermal expansion. This impacts circuit performance. This article develops a procedure that performs a performance analysis of 3D DRAMs, capturing the impact of both layout-Aware stress and layout-independent stress on parameters such as latency, leakage power, refresh power, area, and bus delay. The approach first proposes a semianalytical stress analysis method for the entire 3D DRAM structure, capturing the stress induced by through-siliconvias (TSVs), micro bumps, package bumps, and warpage. Next, this stress is translated to variations in device mobility and threshold voltage, after which analytical models for latency, leakage power, and refresh power are derived. Finally, a complete analysis of performance variations is performed for various 3D DRAM layout configurations to assess the impact of layout-dependent stress. We explore the use of alternative flexible package substrate options to mitigate the performance impact of stress. Specifically, we explore the use of an alternative bendable package substrate made of polyimide to reduce warpage-induced stress, and show that it reduces stress-induced variations and improves the performance metrics for stacked 3D DRAMs.

Original languageEnglish (US)
Article number57
JournalACM Transactions on Design Automation of Electronic Systems
Volume24
Issue number5
DOIs
StatePublished - Oct 2019

Bibliographical note

Funding Information:
This work was supported in part by the NSF under award CCF-1421606. A preliminary and abridged version of this article is published in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 645-650, 2017. Authors’ addresses: T. Li and S. S. Sapatnekar, University of Minnesota, 200 Union Street SE, Minneapolis, MN, 55455, USA; emails: {lixx2967, sachin}@umn.edu. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. © 2019 Association for Computing Machinery. 1084-4309/2019/06-ART51 $15.00 https://doi.org/10.1145/3331527

Keywords

  • 3D DRAMs
  • Stress
  • finite element analysis
  • package substrate
  • performance analysis
  • wide I/O

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