Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs

Tengtao Li; Sachin S. Sapatnekar

doi:10.1109/ICCAD.2017.8203838

Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

3D-stacked wide I/O DRAM can significantly increase cell density and bandwidth while also lowering power consumption. However, 3D structures experience significant thermomechanical stress, which impacts circuit performance. This paper develops a procedure that performs a full performance analysis of 3D DRAMs, including latency, leakage power, refresh power, and area, while incorporating the effects of both layout-aware stress and layout-independent stress. The approach first proposes an analytic stress analysis method for the entire 3D DRAM structure, capturing the stress induced by TSVs, micro bumps, package bumps and warpage. Next, this stress is translated to variations in device mobility and threshold voltage, after which analytical models for latency, leakage power, and refresh power are derived. Finally, a complete analysis of performance variations is performed for various 3D DRAM layout configurations to assess the impact of layout-dependent stress.

Original language	English (US)
Title of host publication	2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	645-650
Number of pages	6
ISBN (Electronic)	9781538630938
DOIs	https://doi.org/10.1109/ICCAD.2017.8203838
State	Published - Dec 13 2017
Externally published	Yes
Event	36th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017 - Irvine, United States Duration: Nov 13 2017 → Nov 16 2017

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Volume	2017-November
ISSN (Print)	1092-3152

Other

Other	36th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017
Country	United States
City	Irvine
Period	11/13/17 → 11/16/17

Bibliographical note

Funding Information:
0This work was supported in part by the NSF under award CCF-1421606.

Funding Information:
This work was supported in part by the NSF under award CCF-1421606.

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Li, T., & Sapatnekar, S. S. (2017). Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. In 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017 (pp. 645-650). (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2017-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2017.8203838

Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. / Li, Tengtao; Sapatnekar, Sachin S.

2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 645-650 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2017-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, T & Sapatnekar, SS 2017, Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. in 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, vol. 2017-November, Institute of Electrical and Electronics Engineers Inc., pp. 645-650, 36th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, United States, 11/13/17. https://doi.org/10.1109/ICCAD.2017.8203838

Li T, Sapatnekar SS. Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. In 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 645-650. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). https://doi.org/10.1109/ICCAD.2017.8203838

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abstract = "3D-stacked wide I/O DRAM can significantly increase cell density and bandwidth while also lowering power consumption. However, 3D structures experience significant thermomechanical stress, which impacts circuit performance. This paper develops a procedure that performs a full performance analysis of 3D DRAMs, including latency, leakage power, refresh power, and area, while incorporating the effects of both layout-aware stress and layout-independent stress. The approach first proposes an analytic stress analysis method for the entire 3D DRAM structure, capturing the stress induced by TSVs, micro bumps, package bumps and warpage. Next, this stress is translated to variations in device mobility and threshold voltage, after which analytical models for latency, leakage power, and refresh power are derived. Finally, a complete analysis of performance variations is performed for various 3D DRAM layout configurations to assess the impact of layout-dependent stress.",

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Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs

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