Abstract
In this chapter, we proposed a low-cost and energy -efficient design for hardware implementation of CNNs. LD deterministic bit -streams and simple standard AND gates are used to perform fast and accurate multiplication operations in the first layer of the NN. Compared to prior random bit -stream -based designs, the proposed design achieves a lower misclassification rate for the same processing time. Evaluating LeNet5 NN with MINIST dataset as the input, the proposed design achieved the same classification rate as the conventional fixed-point binary design with 70% saving in the energy consumption of the first convolutional layer. If accepting slight inaccuracies, higher energy savings are also feasible by processing shorter bit -streams.
| Original language | English (US) |
|---|---|
| Title of host publication | Hardware Architectures for Deep Learning |
| Publisher | Institution of Engineering and Technology |
| Pages | 79-94 |
| Number of pages | 16 |
| ISBN (Electronic) | 9781785617683 |
| DOIs | |
| State | Published - Jan 1 2020 |
Bibliographical note
Publisher Copyright:© The Institution of Engineering and Technology 2020.
Keywords
- AND gates
- CNN
- Convolutional neural nets
- Fixed-point binary design
- LD deterministic bit-streams
- LeNet5 NN
- Logic design
- Logic gates
- MINIST dataset
- Multiplication operations
- Optical character recognition
- Stochastic-binary convolutional neural networks