Stochastic-binary convolutional neural networks with deterministic bit-streams

  • M. Hassan Najafi
  • , S. Rasoul Faraji
  • , Bingzhe Li
  • , David J. Lilja
  • , Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

In this chapter, we proposed a low-cost and energy -efficient design for hardware implementation of CNNs. LD deterministic bit -streams and simple standard AND gates are used to perform fast and accurate multiplication operations in the first layer of the NN. Compared to prior random bit -stream -based designs, the proposed design achieves a lower misclassification rate for the same processing time. Evaluating LeNet5 NN with MINIST dataset as the input, the proposed design achieved the same classification rate as the conventional fixed-point binary design with 70% saving in the energy consumption of the first convolutional layer. If accepting slight inaccuracies, higher energy savings are also feasible by processing shorter bit -streams.

Original languageEnglish (US)
Title of host publicationHardware Architectures for Deep Learning
PublisherInstitution of Engineering and Technology
Pages79-94
Number of pages16
ISBN (Electronic)9781785617683
DOIs
StatePublished - Jan 1 2020

Bibliographical note

Publisher Copyright:
© The Institution of Engineering and Technology 2020.

Keywords

  • AND gates
  • CNN
  • Convolutional neural nets
  • Fixed-point binary design
  • LD deterministic bit-streams
  • LeNet5 NN
  • Logic design
  • Logic gates
  • MINIST dataset
  • Multiplication operations
  • Optical character recognition
  • Stochastic-binary convolutional neural networks

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