Stochastic and topologically aware electromigration analysis for clock skew

Palkesh Jain; Sachin S. Sapatnekar; Jordi Cortadella

doi:10.1109/IRPS.2015.7112714

Stochastic and topologically aware electromigration analysis for clock skew

Palkesh Jain
, Sachin S. Sapatnekar
, Jordi Cortadella

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

An important link between individual component-level EM failures and the failure of the associated system is established in this work. Conventional EM methodologies are based on the weakest link assumption, which deems the entire system to fail as soon as the first component in the system fails. With a highly redundant circuit topology - that of a clock grid - we present algorithms for EM assessment, which allow us to incorporate and quantify the benefit from system redundancies. We demonstrate that unless such an analysis is performed, chip lifetimes are underestimated by over 2x.

Original language	English (US)
Title of host publication	2015 IEEE International Reliability Physics Symposium, IRPS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	3D41-3D46
ISBN (Electronic)	9781467373623
DOIs	https://doi.org/10.1109/IRPS.2015.7112714
State	Published - May 26 2015
Event	IEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States Duration: Apr 19 2015 → Apr 23 2015

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
Volume	2015-May
ISSN (Print)	1541-7026

Other

Other	IEEE International Reliability Physics Symposium, IRPS 2015
Country/Territory	United States
City	Monterey
Period	4/19/15 → 4/23/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

clock
clock-grid
delay-degradation
electromigration
skew

Publisher link

10.1109/IRPS.2015.7112714

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Jain, P., Sapatnekar, S. S., & Cortadella, J. (2015). Stochastic and topologically aware electromigration analysis for clock skew. In 2015 IEEE International Reliability Physics Symposium, IRPS 2015 (pp. 3D41-3D46). Article 7112714 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2015-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2015.7112714

Stochastic and topologically aware electromigration analysis for clock skew. / Jain, Palkesh; Sapatnekar, Sachin S.; Cortadella, Jordi.
2015 IEEE International Reliability Physics Symposium, IRPS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 3D41-3D46 7112714 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2015-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jain, P, Sapatnekar, SS & Cortadella, J 2015, Stochastic and topologically aware electromigration analysis for clock skew. in 2015 IEEE International Reliability Physics Symposium, IRPS 2015., 7112714, IEEE International Reliability Physics Symposium Proceedings, vol. 2015-May, Institute of Electrical and Electronics Engineers Inc., pp. 3D41-3D46, IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, United States, 4/19/15. https://doi.org/10.1109/IRPS.2015.7112714

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AB - An important link between individual component-level EM failures and the failure of the associated system is established in this work. Conventional EM methodologies are based on the weakest link assumption, which deems the entire system to fail as soon as the first component in the system fails. With a highly redundant circuit topology - that of a clock grid - we present algorithms for EM assessment, which allow us to incorporate and quantify the benefit from system redundancies. We demonstrate that unless such an analysis is performed, chip lifetimes are underestimated by over 2x.

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ER -

Stochastic and topologically aware electromigration analysis for clock skew

Abstract

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