Abstract
Timing optimization is a critical component of deep submicrometer design and buffer insertion is an essential technique for achieving timing closure. This work studies buffer insertion under the constraint that the buffers either: 1) avoid blockages or 2) are contained within preassigned buffer bay regions. We propose a general Steiner-tree formulation to drive this application and present a maze-routing-based heuristic that either avoids blockages or finds buffer bays. We show that the combination of our Steiner-tree optimization with leading-edge buffer-insertion techniques leads to effective solutions on industry designs.
Original language | English (US) |
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Pages (from-to) | 556-562 |
Number of pages | 7 |
Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Volume | 20 |
Issue number | 4 |
DOIs | |
State | Published - Apr 2001 |
Keywords
- Buffer insertion
- Deep submicrometer
- Interconnect
- Performance optimization
- Physical design
- Routing
- VLSI