Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages

Drew C. Ness; David J. Lilja

doi:10.1145/1366110.1366181

Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages

Drew C. Ness, David J. Lilja

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Radiation induced single-event upsets are becoming an increasing issue for designers due to the impact on overall design reliability. This paper presents a method for translating probabilistic information from lower levels in the design hierarchy into efficient, fast, and useful tools at higher levels. This method allows designers to incorporate soft error reliability analysis into the verification process at greatly reduced simulation expense with high accuracy. We also include metrics to estimate the error in the method. Results from both abstracted verification simulations and Verilog soft error simulations are presented. Our method bridges a gap between low level reliability measurements and high level reliability simulations.

Original language	English (US)
Title of host publication	GLSVLSI 2008
Subtitle of host publication	Proceedings of the 2008 ACM Great Lakes Symposium on VLSI
Pages	297-302
Number of pages	6
DOIs	https://doi.org/10.1145/1366110.1366181
State	Published - 2008
Event	GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, United States Duration: Mar 4 2008 → Mar 6 2008

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

Other	GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
Country/Territory	United States
City	Orlando, FL
Period	3/4/08 → 3/6/08

Keywords

Fault distribution
Reliability analysis
SER
SEU

Publisher link

10.1145/1366110.1366181

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Ness, D. C., & Lilja, D. J. (2008). Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages. In GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI (pp. 297-302). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1366110.1366181

Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages. / Ness, Drew C.; Lilja, David J.
GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI. 2008. p. 297-302 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ness, DC & Lilja, DJ 2008, Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages. in GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 297-302, GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, FL, United States, 3/4/08. https://doi.org/10.1145/1366110.1366181

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abstract = "Radiation induced single-event upsets are becoming an increasing issue for designers due to the impact on overall design reliability. This paper presents a method for translating probabilistic information from lower levels in the design hierarchy into efficient, fast, and useful tools at higher levels. This method allows designers to incorporate soft error reliability analysis into the verification process at greatly reduced simulation expense with high accuracy. We also include metrics to estimate the error in the method. Results from both abstracted verification simulations and Verilog soft error simulations are presented. Our method bridges a gap between low level reliability measurements and high level reliability simulations.",

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AB - Radiation induced single-event upsets are becoming an increasing issue for designers due to the impact on overall design reliability. This paper presents a method for translating probabilistic information from lower levels in the design hierarchy into efficient, fast, and useful tools at higher levels. This method allows designers to incorporate soft error reliability analysis into the verification process at greatly reduced simulation expense with high accuracy. We also include metrics to estimate the error in the method. Results from both abstracted verification simulations and Verilog soft error simulations are presented. Our method bridges a gap between low level reliability measurements and high level reliability simulations.

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Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages

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