We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parameter variations, using a method based on principal component analysis. The method uses a PERT-like circuit graph traversal, and has a run-time that is linear in the number of gates and interconnects, as well as the number of grid partitions used to model spatial correlations. On average, the mean and standard deviation values computed by our method have errors of 0.2% and 0.9%, respectively, in comparison with a Monte Carlo simulation.
|Original language||English (US)|
|Number of pages||5|
|Journal||IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers|
|State||Published - Dec 26 2003|
|Event||IEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers - San Jose, CA, United States|
Duration: Nov 9 2003 → Nov 13 2003