Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

Sarvesh Bhardwaj; Yu Caot; Sarma Vrudhula

doi:10.1145/1118299.1118513

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

Sarvesh Bhardwaj, Yu Caot, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Scopus citations

Abstract

This paper¹ proposes a novel methodology for statistical leakage minimization of digital circuits. A function of mean and variance of the circuit leakage is minimized with constraint on α-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables can provide significant amount of power savings. The leakage minimization problem is formulated as a multivariable convex optimization problem. We demonstrate that statistical optimization can lead to more than 37% savings in nominal leakage compared to worst-case techniques that perform only gate sizing.

Original language	English (US)
Title of host publication	Proceedings of the ASP-DAC 2006
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2006
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	953-958
Number of pages	6
ISBN (Print)	0780394518, 9780780394513
DOIs	https://doi.org/10.1145/1118299.1118513
State	Published - 2006
Externally published	Yes
Event	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan Duration: Jan 24 2006 → Jan 27 2006

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2006

Other

Other	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Country/Territory	Japan
City	Yokohama
Period	1/24/06 → 1/27/06

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10.1145/1118299.1118513

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Bhardwaj, S., Caot, Y., & Vrudhula, S. (2006). Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 953-958). Article 1594809 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1118299.1118513

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. / Bhardwaj, Sarvesh; Caot, Yu; Vrudhula, Sarma.
Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., 2006. p. 953-958 1594809 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Bhardwaj, S, Caot, Y & Vrudhula, S 2006, Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. in Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006., 1594809, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2006, Institute of Electrical and Electronics Engineers Inc., pp. 953-958, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, Yokohama, Japan, 1/24/06. https://doi.org/10.1145/1118299.1118513

Bhardwaj S, Caot Y, Vrudhula S. Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc. 2006. p. 953-958. 1594809. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/1118299.1118513

Bhardwaj, Sarvesh ; Caot, Yu ; Vrudhula, Sarma. / Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., 2006. pp. 953-958 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

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abstract = "This paper1 proposes a novel methodology for statistical leakage minimization of digital circuits. A function of mean and variance of the circuit leakage is minimized with constraint on α-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables can provide significant amount of power savings. The leakage minimization problem is formulated as a multivariable convex optimization problem. We demonstrate that statistical optimization can lead to more than 37% savings in nominal leakage compared to worst-case techniques that perform only gate sizing.",

author = "Sarvesh Bhardwaj and Yu Caot and Sarma Vrudhula",

year = "2006",

doi = "10.1145/1118299.1118513",

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series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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AB - This paper1 proposes a novel methodology for statistical leakage minimization of digital circuits. A function of mean and variance of the circuit leakage is minimized with constraint on α-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables can provide significant amount of power savings. The leakage minimization problem is formulated as a multivariable convex optimization problem. We demonstrate that statistical optimization can lead to more than 37% savings in nominal leakage compared to worst-case techniques that perform only gate sizing.

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Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

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