Statistical generic and chip-specific skew assignment for improving timing yield of FPGAs

Satish Sivaswamy, Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper presents a technique to fix timing violations caused by process variations in FPGAs by adjusting the clock skews of flip-flops. This involves making the clock distribution network tunable by adding programmable delay elements to compensate for variations. We propose generic as well as chip-specific skew assignment schemes that are robust to variations. The two proposed schemes result in recovering about 80% and 82% of the failed chips respectively with conservative timing constraints. With more aggressive constraints, the corresponding numbers are 69% and 77% respectively. Our technique causes a 39% increase in the number of chips in the fast bin when speed-binning is performed. The area and power overhead associated with this technique are 3.5% and 5.6% respectively.

Original languageEnglish (US)
Title of host publicationProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
Pages429-434
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
Duration: Aug 27 2007Aug 29 2007

Publication series

NameProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2007 International Conference on Field Programmable Logic and Applications, FPL
CountryNetherlands
CityAmsterdam
Period8/27/078/29/07

Fingerprint Dive into the research topics of 'Statistical generic and chip-specific skew assignment for improving timing yield of FPGAs'. Together they form a unique fingerprint.

Cite this