Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique

Saurabh Kumar, Minki Cho, Luke Eversen, Hoonki Kim, Qianying Tang, Paul Mazanec, Pascal Meinerzhagen, Andres Malavasi, Dan Lake, Carlos Tokunaga, Heather Quinn, Muhammad Khellah, James Tschanz, Shekhar Borkar, Vivek De, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel BSC circuit with tunable current starved buffers demonstrates higher sensitivity, scalability & accurate statistical characterization of radiation-induced SET pulse waveforms & flip-flop SER in 14nm tri-gate CMOS, thus enabling improved SER estimation & analysis for a range of supply voltages including NTV.

Original languageEnglish (US)
Title of host publication2017 Symposium on VLSI Circuits, VLSI Circuits 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC114-C115
ISBN (Electronic)9784863486065
DOIs
StatePublished - Aug 10 2017
Event31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan
Duration: Jun 5 2017Jun 8 2017

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other31st Symposium on VLSI Circuits, VLSI Circuits 2017
CountryJapan
CityKyoto
Period6/5/176/8/17

Bibliographical note

Funding Information:
change with supply voltage as well, as expected. The original SET pulse waveforms as well as the joint distributions of pulse amplitude & full width half max (FWHM) are reconstructed for different supply voltages from the pulse width measurements for a range of detection thresholds (buffer starving voltages) at each supply voltage (Fig. 6). Measured SEU/MBU cross-section versus supply voltage results for the flip-flops embedded in the BSC array scan chain, as shown in Fig. 6, confirm the inverse dependence of SER on supply voltage. These measured SET pulse distributions can be used in conjunction with the measured SEU/MBU cross-section results to calibrate and validate accuracies of predictive SER & QCrit models for different circuits across a range of voltages including NTV, thus paving the way for full chip level SER estimation and analysis. Acknowledgements The authors thank R. Corkran, C. Roberts and N. Seifert for their help. This research was, in part, funded by the U.S. government. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. government. References [1] N. Seifert, TNS, 2015 [2] S. Lee, IRPS, 2015 [3] T. D. Loveless, IEEE TNS, 2012 [4] J. Furuta, IRPS, 2011.

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