Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs

Satish Sivaswamy, Kia Bazargan

Research output: Contribution to journalArticlepeer-review

13 Scopus citations

Abstract

With constant scaling of process technologies, chip design is becoming increasingly difficult due to process variations. The FPGA community has only recently started focusing on the effects of variations. In this work we present a statistical analysis to compare the effects of variations on designs mapped to FPGAs and ASICs. We also present CAD and architecture techniques to mitigate the impact of variations. First we present a variation-aware router that optimizes statistical criticality. We then propose a modification to the clock network to deliver programmable skews to different flip-flops. Finally, we combine the two techniques and the result is a 9x reduction in yield loss that translates to a 12% improvement in timing yield. When the desired timing yield is set to 99%, our combined statistical routing and skew assignment technique results in a delay improvement of about 10% over a purely deterministic approach.

Original languageEnglish (US)
Pages (from-to)1-35
Number of pages35
JournalACM Transactions on Reconfigurable Technology and Systems
Volume1
Issue number1
DOIs
StatePublished - Mar 1 2008

Keywords

  • Algorithms
  • Design
  • Performance
  • Statistical timing analysis
  • routing
  • skew assignment

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