Statistical analysis and design of HARP FPGAs

Gang Wang; Satish Sivaswamy; Cristinel Ababei; Kia Bazargan; Ryan Kastner; Elaheh Bozorgzadeh

doi:10.1109/TCAD.2005.859485

Statistical analysis and design of HARP FPGAs

Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

15 Scopus citations

Abstract

Modern field programmable gate array (FPGA) architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such a great flexibility comes at a high cost in terms of area, delay, and power. The authors propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. The result is an about a 30% reduction in leakage power consumption, a 5% smaller area, and 20% shorter delays, which translates to a 25% increase in the clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced.

Original language	English (US)
Article number	1677693
Pages (from-to)	2088-2101
Number of pages	14
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	25
Issue number	10
DOIs	https://doi.org/10.1109/TCAD.2005.859485
State	Published - Oct 2006

Bibliographical note

Funding Information:
Manuscript received April 12, 2005; revised August 2, 2005. This work was supported in part by the National Science Foundation (NSF) under Contract CAREER CCF-0347891. This paper was recommended by Associate Editor C. J. Alpert.

Keywords

Architecture
Field programmable gate arrays
Integrated circuits
Routing

Publisher link

10.1109/TCAD.2005.859485

Find It

Find It at U of M Libraries

Cite this

@article{b0b9be2b85bb4607a99e09c30aa7ec7e,

title = "Statistical analysis and design of HARP FPGAs",

abstract = "Modern field programmable gate array (FPGA) architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such a great flexibility comes at a high cost in terms of area, delay, and power. The authors propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. The result is an about a 30% reduction in leakage power consumption, a 5% smaller area, and 20% shorter delays, which translates to a 25% increase in the clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced.",

keywords = "Architecture, Field programmable gate arrays, Integrated circuits, Routing",

author = "Gang Wang and Satish Sivaswamy and Cristinel Ababei and Kia Bazargan and Ryan Kastner and Elaheh Bozorgzadeh",

note = "Funding Information: Manuscript received April 12, 2005; revised August 2, 2005. This work was supported in part by the National Science Foundation (NSF) under Contract CAREER CCF-0347891. This paper was recommended by Associate Editor C. J. Alpert.",

year = "2006",

month = oct,

doi = "10.1109/TCAD.2005.859485",

language = "English (US)",

volume = "25",

pages = "2088--2101",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - Statistical analysis and design of HARP FPGAs

AU - Wang, Gang

AU - Sivaswamy, Satish

AU - Ababei, Cristinel

AU - Bazargan, Kia

AU - Kastner, Ryan

AU - Bozorgzadeh, Elaheh

N1 - Funding Information: Manuscript received April 12, 2005; revised August 2, 2005. This work was supported in part by the National Science Foundation (NSF) under Contract CAREER CCF-0347891. This paper was recommended by Associate Editor C. J. Alpert.

PY - 2006/10

Y1 - 2006/10

N2 - Modern field programmable gate array (FPGA) architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such a great flexibility comes at a high cost in terms of area, delay, and power. The authors propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. The result is an about a 30% reduction in leakage power consumption, a 5% smaller area, and 20% shorter delays, which translates to a 25% increase in the clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced.

AB - Modern field programmable gate array (FPGA) architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such a great flexibility comes at a high cost in terms of area, delay, and power. The authors propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. The result is an about a 30% reduction in leakage power consumption, a 5% smaller area, and 20% shorter delays, which translates to a 25% increase in the clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced.

KW - Architecture

KW - Field programmable gate arrays

KW - Integrated circuits

KW - Routing

UR - http://www.scopus.com/inward/record.url?scp=33748308927&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33748308927&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2005.859485

DO - 10.1109/TCAD.2005.859485

M3 - Article

AN - SCOPUS:33748308927

VL - 25

SP - 2088

EP - 2101

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 10

M1 - 1677693

ER -

Statistical analysis and design of HARP FPGAs

Abstract

Bibliographical note

Keywords

Publisher link

Find It

Other files and links

Fingerprint

Cite this