TY - JOUR
T1 - Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm
AU - Alvarez, Anastacia B.
AU - Zhao, Wenfeng
AU - Alioto, Massimo
PY - 2016/3
Y1 - 2016/3
N2 - A novel class of mono-stable static physically unclonable functions (PUFs) for secure key generation and chip identification is proposed. The fundamental concept is demonstrated through a 65 nm prototype that contains two different implementations, as well as several previously proposed PUFs to enable a fair comparison at iso-technology. From a statistical quality viewpoint, the achieved reproducibility and uniqueness are quantified by an intra-PUF Hamming distance (HD) lower than 1 and an inter-PUF HD of 128.35, for a 256-bit PUF output key. The keys generated by the proposed PUF pass all applicable NIST randomness tests. The measured energy per bit is as low as 15 fJ/bit. Native unstable bits are less than 2% at nominal conditions, less than 5% at 0.6-1 V and less than 6% in worst case scenario of 0.6 V voltage and 85 °C temperature, before applying any further post-silicon technique for stability enhancement.
AB - A novel class of mono-stable static physically unclonable functions (PUFs) for secure key generation and chip identification is proposed. The fundamental concept is demonstrated through a 65 nm prototype that contains two different implementations, as well as several previously proposed PUFs to enable a fair comparison at iso-technology. From a statistical quality viewpoint, the achieved reproducibility and uniqueness are quantified by an intra-PUF Hamming distance (HD) lower than 1 and an inter-PUF HD of 128.35, for a 256-bit PUF output key. The keys generated by the proposed PUF pass all applicable NIST randomness tests. The measured energy per bit is as low as 15 fJ/bit. Native unstable bits are less than 2% at nominal conditions, less than 5% at 0.6-1 V and less than 6% in worst case scenario of 0.6 V voltage and 85 °C temperature, before applying any further post-silicon technique for stability enhancement.
KW - Current mirror
KW - hardware security
KW - physically unclonable functions (PUFs)
KW - process variation
KW - secure chip identification
UR - http://www.scopus.com/inward/record.url?scp=84957647470&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84957647470&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2015.2506641
DO - 10.1109/JSSC.2015.2506641
M3 - Article
AN - SCOPUS:84957647470
VL - 51
SP - 763
EP - 775
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 3
M1 - 7397840
ER -