Standby power optimization via transistor sizing and dual threshold voltage assignment

Mahesh Ketkar, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a novel enumerative approach, with provable and efficient pruning techniques, for dual threshold voltage (Vt) assignment at the transistor level. Since the use of low Vt may entail a substantial increase in leakage power, we formulate the problem as one of combined optimization for leakage-delay tradeoffs under Vt optimization and sizing. Based on an analysis of the effects of these two transforms on the delay and leakage, we justify a two-step procedure for performing this optimization. Results are presented on the ISCAS85 benchmark suite favorably comparing our approach with an existing sensitivity-based optimizer.

Original languageEnglish (US)
Pages (from-to)375-378
Number of pages4
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
DOIs
StatePublished - Jan 1 2002

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