TY - GEN
T1 - Staggered core activation
T2 - 34th Annual Custom Integrated Circuits Conference, CICC 2012
AU - Paul, Ayan
AU - Amrein, Matt
AU - Gupta, Saket
AU - Vinod, Arvind
AU - Arun, Abhishek
AU - Sapatnekar, Sachin S
AU - Kim, Chris H.
PY - 2012/11/26
Y1 - 2012/11/26
N2 - In order to reduce the impact of resonant supply noise on processor performance, a simple, fully-digital and scalable technique based on staggering the activation time of the cores sharing the same power domain in a multi-core multi-power domain processor is presented. Measurement data from a 65nm test chip shows an Fmax improvement as large as 20% in a 3-core configuration. This is one of the first approaches to utilize the architecture level behavior for mitigating resonant noise issues in a multi-core multi-power domain processor.
AB - In order to reduce the impact of resonant supply noise on processor performance, a simple, fully-digital and scalable technique based on staggering the activation time of the cores sharing the same power domain in a multi-core multi-power domain processor is presented. Measurement data from a 65nm test chip shows an Fmax improvement as large as 20% in a 3-core configuration. This is one of the first approaches to utilize the architecture level behavior for mitigating resonant noise issues in a multi-core multi-power domain processor.
UR - http://www.scopus.com/inward/record.url?scp=84869387621&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84869387621&partnerID=8YFLogxK
U2 - 10.1109/CICC.2012.6330673
DO - 10.1109/CICC.2012.6330673
M3 - Conference contribution
AN - SCOPUS:84869387621
SN - 9781467315555
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
Y2 - 9 September 2012 through 12 September 2012
ER -