Staggered core activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors

Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S Sapatnekar, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In order to reduce the impact of resonant supply noise on processor performance, a simple, fully-digital and scalable technique based on staggering the activation time of the cores sharing the same power domain in a multi-core multi-power domain processor is presented. Measurement data from a 65nm test chip shows an Fmax improvement as large as 20% in a 3-core configuration. This is one of the first approaches to utilize the architecture level behavior for mitigating resonant noise issues in a multi-core multi-power domain processor.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOIs
StatePublished - Nov 26 2012
Event34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States
Duration: Sep 9 2012Sep 12 2012

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other34th Annual Custom Integrated Circuits Conference, CICC 2012
CountryUnited States
CitySan Jose, CA
Period9/9/129/12/12

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    Paul, A., Amrein, M., Gupta, S., Vinod, A., Arun, A., Sapatnekar, S. S., & Kim, C. H. (2012). Staggered core activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. In Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012 [6330673] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2012.6330673