Stack sizing for optimal current drivability in subthreshold circuits

John Keane, Hanyong Eom, Tae Hyoung Kim, Sachin Sapatnekar, Chris Kim

Research output: Contribution to journalArticlepeer-review

21 Scopus citations


Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in strong inversion. This presents new challenges in design optimization, particularly in complex gates with stacks of transistors. In this paper, we present a framework for choosing the optimal transistor stack sizing factors in terms of current drivability for subthreshold designs. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current drivability. Simulation results show that our framework provides a performance benefit ranging up to more than 10% in certain critical paths.

Original languageEnglish (US)
Article number4469919
Pages (from-to)598-602
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number5
StatePublished - May 2008


  • Logical effort
  • Subthreshold logic
  • Ultra low power design


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