SrSnO3Field-Effect Transistors with Recessed Gate Electrodes

V. R. Saran Kumar Chaganti, Tristan K. Truttmann, Fengdeng Liu, Bharat Jalan, Steven J. Koester

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

Fabrication of gate-recessed SrSnO3 (SSO) metal-semiconductor field-effect transistors (MESFETs) with Ni Schottky gates is reported on bi-layer epitaxial SSO films with a thin heavily-doped cap layer. Devices with 0.5-μm gate length showed enhancement-mode behavior with a saturation drain current, IDSAT , of 33 mA/mm and peak transconductance, gm,max , of 65 mS/mm. The gm,max value is a roughly × improvement over control devices fabricated on single-layer films. Gate-recessed SSO MESFETs with Pt Schottky gates were also explored on the bi-layer films. Devices with 1-μm gate length displayed IDSAT =133 mA/mm and gm,max =73 mS/mm, after thermal annealing.

Original languageEnglish (US)
Article number9145756
Pages (from-to)1428-1431
Number of pages4
JournalIEEE Electron Device Letters
Volume41
Issue number9
DOIs
StatePublished - Sep 2020

Bibliographical note

Funding Information:
Manuscript received July 7, 2020; revised July 18, 2020; accepted July 19, 2020. Date of publication July 21, 2020; date of current version August 26, 2020. This work was primarily supported by the Air Force Office of Scientific Research through Award Number FA9550-19-1-0245, in part by the National Science Foundation (NSF) through the University of Minnesota MRSEC under Award Number DMR-2011401, and in part by the NSF through Award Number DMR-1741801. Portions of this work were conducted in the Minnesota Nano Center, which was supported by the NSF through the National Nano Coordinated Infrastructure under Award Number ECCS-1542202. The review of this letter was arranged by Editor A. Chin. (Corresponding authors: Steven J. Koester; Bharat Jalan.) V. R. Saran Kumar Chaganti and Steven J. Koester are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: skoester@umn.edu).

Publisher Copyright:
© 1980-2012 IEEE.

Keywords

  • gate recess
  • MESFET
  • perovskites
  • stannate

MRSEC Support

  • Partial

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