SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data

Xiaofei Wang, Weichao Xu, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Asymmetric BTI aging in circuit paths has shown to cause a time dependent shift in the signal's duty cycle, affecting the performance of circuits such as low power SRAMs whose operation rely on both the positive and negative edges of the clock signal. In this work, we propose the first known on-chip reliability monitor to accurately characterize the impact of asymmetric BTI on SRAM read speed. Statistical data collected from test chip built in a 32nm high-k metal-gate technology shows that (i) the average SRAM read frequency decreases with stress while its variation increases with stress and (ii) both μ and σ of read frequency shift follow a power law dependence on stress time. These observations point to the impact of SRAM peripheral circuit aging on read performance, and the utility of the proposed monitor for characterizing circuit level reliability concerns.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479932863
DOIs
StatePublished - Nov 4 2014
Event36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States
Duration: Sep 15 2014Sep 17 2014

Publication series

NameProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Other

Other36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
CountryUnited States
CitySan Jose
Period9/15/149/17/14

Keywords

  • BTI
  • SRAM
  • asymmetric aging
  • peripheral circuits
  • read degradation

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