Asymmetric BTI aging in circuit paths has shown to cause a time dependent shift in the signal's duty cycle, affecting the performance of circuits such as low power SRAMs whose operation rely on both the positive and negative edges of the clock signal. In this work, we propose the first known on-chip reliability monitor to accurately characterize the impact of asymmetric BTI on SRAM read speed. Statistical data collected from test chip built in a 32nm high-k metal-gate technology shows that (i) the average SRAM read frequency decreases with stress while its variation increases with stress and (ii) both μ and σ of read frequency shift follow a power law dependence on stress time. These observations point to the impact of SRAM peripheral circuit aging on read performance, and the utility of the proposed monitor for characterizing circuit level reliability concerns.
|Original language||English (US)|
|Title of host publication||Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Nov 4 2014|
|Event||36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States|
Duration: Sep 15 2014 → Sep 17 2014
|Name||Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014|
|Other||36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014|
|Period||9/15/14 → 9/17/14|
Bibliographical notePublisher Copyright:
© 2014 IEEE.
- asymmetric aging
- peripheral circuits
- read degradation