SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data

Xiaofei Wang; Weichao Xu; Chris H. Kim

doi:10.1109/CICC.2014.6946132

SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data

Xiaofei Wang, Weichao Xu, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

Asymmetric BTI aging in circuit paths has shown to cause a time dependent shift in the signal's duty cycle, affecting the performance of circuits such as low power SRAMs whose operation rely on both the positive and negative edges of the clock signal. In this work, we propose the first known on-chip reliability monitor to accurately characterize the impact of asymmetric BTI on SRAM read speed. Statistical data collected from test chip built in a 32nm high-k metal-gate technology shows that (i) the average SRAM read frequency decreases with stress while its variation increases with stress and (ii) both μ and σ of read frequency shift follow a power law dependence on stress time. These observations point to the impact of SRAM peripheral circuit aging on read performance, and the utility of the proposed monitor for characterizing circuit level reliability concerns.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479932863
DOIs	https://doi.org/10.1109/CICC.2014.6946132
State	Published - Nov 4 2014
Event	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States Duration: Sep 15 2014 → Sep 17 2014

Publication series

Name	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Other

Other	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
Country/Territory	United States
City	San Jose
Period	9/15/14 → 9/17/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

BTI
SRAM
asymmetric aging
peripheral circuits
read degradation

Publisher link

10.1109/CICC.2014.6946132

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Wang, X., Xu, W., & Kim, C. H. (2014). SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 Article 6946132 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2014.6946132

SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data. / Wang, Xiaofei; Xu, Weichao; Kim, Chris H.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6946132 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, X, Xu, W & Kim, CH 2014, SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014., 6946132, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, Institute of Electrical and Electronics Engineers Inc., 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014, San Jose, United States, 9/15/14. https://doi.org/10.1109/CICC.2014.6946132

Wang X, Xu W, Kim CH. SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6946132. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). doi: 10.1109/CICC.2014.6946132

Wang, Xiaofei ; Xu, Weichao ; Kim, Chris H. / SRAM read performance degradation under asymmetric NBTI and PBTI stress : Characterization vehicle and statistical aging data. Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

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abstract = "Asymmetric BTI aging in circuit paths has shown to cause a time dependent shift in the signal's duty cycle, affecting the performance of circuits such as low power SRAMs whose operation rely on both the positive and negative edges of the clock signal. In this work, we propose the first known on-chip reliability monitor to accurately characterize the impact of asymmetric BTI on SRAM read speed. Statistical data collected from test chip built in a 32nm high-k metal-gate technology shows that (i) the average SRAM read frequency decreases with stress while its variation increases with stress and (ii) both μ and σ of read frequency shift follow a power law dependence on stress time. These observations point to the impact of SRAM peripheral circuit aging on read performance, and the utility of the proposed monitor for characterizing circuit level reliability concerns.",

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AB - Asymmetric BTI aging in circuit paths has shown to cause a time dependent shift in the signal's duty cycle, affecting the performance of circuits such as low power SRAMs whose operation rely on both the positive and negative edges of the clock signal. In this work, we propose the first known on-chip reliability monitor to accurately characterize the impact of asymmetric BTI on SRAM read speed. Statistical data collected from test chip built in a 32nm high-k metal-gate technology shows that (i) the average SRAM read frequency decreases with stress while its variation increases with stress and (ii) both μ and σ of read frequency shift follow a power law dependence on stress time. These observations point to the impact of SRAM peripheral circuit aging on read performance, and the utility of the proposed monitor for characterizing circuit level reliability concerns.

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SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data

Abstract

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