Spin-Hall effect MRAM based cache memory: A feasibility study

Jongyeon Kim; Bill Tuohy; Cong Ma; Won Ho Choi; Ibrahim Ahmed; David Lilja; Chris H. Kim

doi:10.1109/DRC.2015.7175583

Spin-Hall effect MRAM based cache memory: A feasibility study

Jongyeon Kim, Bill Tuohy, Cong Ma, Won Ho Choi, Ibrahim Ahmed, David Lilja, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

One of the key objectives of STT-MRAM research has been on minimizing switching current while maintaining the required nonvolatility. To address this challenge, non-traditional MRAMs based on novel switching mechanisms have been proposed. In particular, spin-Hall effect (SHE) which utilizes large spin currents generated in the direction transverse to the charge current have been recently drawing attention [1]. Despite early promises such as lower switching current by means of efficient spin generation (i.e. I_spin/I_charge>100%) and longer device lifetime owing to the decoupled read and write paths, there is still a lack of a comprehensive study for benchmarking SHE-MRAM against other memory technologies. In this work, we explore the trade-off points across different levels of design abstraction (i.e. device, circuit, and architecture) to evaluate the feasibility of SHE-MRAM for large on-die cache memory.

Original language	English (US)
Title of host publication	73rd Annual Device Research Conference, DRC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	117-118
Number of pages	2
ISBN (Electronic)	9781467381345
DOIs	https://doi.org/10.1109/DRC.2015.7175583
State	Published - Aug 3 2015
Event	73rd Annual Device Research Conference, DRC 2015 - Columbus, United States Duration: Jun 21 2015 → Jun 24 2015

Publication series

Name	Device Research Conference - Conference Digest, DRC
Volume	2015-August
ISSN (Print)	1548-3770

Conference

Conference	73rd Annual Device Research Conference, DRC 2015
Country/Territory	United States
City	Columbus
Period	6/21/15 → 6/24/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

Delays
FinFETs
Integrated circuit modeling
Random access memory
Sensors
Tunneling magnetoresistance

Publisher link

10.1109/DRC.2015.7175583

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Kim, J., Tuohy, B., Ma, C., Choi, W. H., Ahmed, I., Lilja, D., & Kim, C. H. (2015). Spin-Hall effect MRAM based cache memory: A feasibility study. In 73rd Annual Device Research Conference, DRC 2015 (pp. 117-118). Article 7175583 (Device Research Conference - Conference Digest, DRC; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DRC.2015.7175583

Spin-Hall effect MRAM based cache memory: A feasibility study. / Kim, Jongyeon; Tuohy, Bill; Ma, Cong et al.
73rd Annual Device Research Conference, DRC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 117-118 7175583 (Device Research Conference - Conference Digest, DRC; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, J, Tuohy, B, Ma, C, Choi, WH, Ahmed, I, Lilja, D & Kim, CH 2015, Spin-Hall effect MRAM based cache memory: A feasibility study. in 73rd Annual Device Research Conference, DRC 2015., 7175583, Device Research Conference - Conference Digest, DRC, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. 117-118, 73rd Annual Device Research Conference, DRC 2015, Columbus, United States, 6/21/15. https://doi.org/10.1109/DRC.2015.7175583

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abstract = "One of the key objectives of STT-MRAM research has been on minimizing switching current while maintaining the required nonvolatility. To address this challenge, non-traditional MRAMs based on novel switching mechanisms have been proposed. In particular, spin-Hall effect (SHE) which utilizes large spin currents generated in the direction transverse to the charge current have been recently drawing attention [1]. Despite early promises such as lower switching current by means of efficient spin generation (i.e. Ispin/Icharge>100%) and longer device lifetime owing to the decoupled read and write paths, there is still a lack of a comprehensive study for benchmarking SHE-MRAM against other memory technologies. In this work, we explore the trade-off points across different levels of design abstraction (i.e. device, circuit, and architecture) to evaluate the feasibility of SHE-MRAM for large on-die cache memory.",

keywords = "Delays, FinFETs, Integrated circuit modeling, Random access memory, Sensors, Tunneling magnetoresistance",

author = "Jongyeon Kim and Bill Tuohy and Cong Ma and Choi, {Won Ho} and Ibrahim Ahmed and David Lilja and Kim, {Chris H.}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 73rd Annual Device Research Conference, DRC 2015 ; Conference date: 21-06-2015 Through 24-06-2015",

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AU - Lilja, David

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Spin-Hall effect MRAM based cache memory: A feasibility study

Abstract

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Keywords

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