Spin-Hall effect MRAM based cache memory: A feasibility study

Jongyeon Kim, Bill Tuohy, Cong Ma, Won Ho Choi, Ibrahim Ahmed, David Lilja, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

One of the key objectives of STT-MRAM research has been on minimizing switching current while maintaining the required nonvolatility. To address this challenge, non-traditional MRAMs based on novel switching mechanisms have been proposed. In particular, spin-Hall effect (SHE) which utilizes large spin currents generated in the direction transverse to the charge current have been recently drawing attention [1]. Despite early promises such as lower switching current by means of efficient spin generation (i.e. Ispin/Icharge>100%) and longer device lifetime owing to the decoupled read and write paths, there is still a lack of a comprehensive study for benchmarking SHE-MRAM against other memory technologies. In this work, we explore the trade-off points across different levels of design abstraction (i.e. device, circuit, and architecture) to evaluate the feasibility of SHE-MRAM for large on-die cache memory.

Original languageEnglish (US)
Title of host publication73rd Annual Device Research Conference, DRC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages117-118
Number of pages2
ISBN (Electronic)9781467381345
DOIs
StatePublished - Aug 3 2015
Event73rd Annual Device Research Conference, DRC 2015 - Columbus, United States
Duration: Jun 21 2015Jun 24 2015

Publication series

NameDevice Research Conference - Conference Digest, DRC
Volume2015-August
ISSN (Print)1548-3770

Conference

Conference73rd Annual Device Research Conference, DRC 2015
CountryUnited States
CityColumbus
Period6/21/156/24/15

Keywords

  • Delays
  • FinFETs
  • Integrated circuit modeling
  • Random access memory
  • Sensors
  • Tunneling magnetoresistance

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