TY - JOUR
T1 - Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
AU - Sathyamurthy, Harsha
AU - Sapatnekar, Sachin S.
AU - Fishburn, John P.
PY - 1995/12/1
Y1 - 1995/12/1
N2 - An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.
AB - An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.
UR - https://www.scopus.com/pages/publications/0029521454
UR - https://www.scopus.com/inward/citedby.url?scp=0029521454&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0029521454
SN - 1092-3152
SP - 467
EP - 470
JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
T2 - Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design
Y2 - 5 November 1995 through 9 November 1995
ER -