An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.
|Original language||English (US)|
|Number of pages||4|
|Journal||IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers|
|State||Published - Dec 1 1995|
|Event||Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA|
Duration: Nov 5 1995 → Nov 9 1995