Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.

Original languageEnglish (US)
Pages (from-to)467-470
Number of pages4
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
StatePublished - Dec 1 1995
EventProceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: Nov 5 1995Nov 9 1995

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