SpeEding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization

Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure described herein utilizes the idea of cycle borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. The theoretical basis for the procedure is developed, a new algorithm for timing analysis of acyclic pipeline circuits with deliberate skew is presented, and a sensitivity-based optimizer is used to solve the sizing + skew problem. Our experimental results verify that the procedure of cycle borrowing using sizing + skew results in a better overall area-delay tradeoff as compared to using sizing alone. Index Terms - Clocks, CMOS digital integrated circuits, design automation, optimization methods, synchronization, very large scale integration.

Original languageEnglish (US)
Pages (from-to)173-182
Number of pages10
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume17
Issue number2
DOIs
StatePublished - Dec 1 1998

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